High electron mobility transistors with charge compensation

ABSTRACT

A variety of high electron mobility transistor structures are provided having charge compensation regions that can extend below the gate electrode through the barrier layer and at least partially through the III-V semiconductor layer. The charge compensation regions include a p-type semiconductor or oxide. In some aspects, the charge compensation regions extend vertically through said barrier layer into said channel layer, wherein said charge-compensation regions are doped with p-type dopants and are placed aside the 2DEG channel and do not overlap vertically with the 2DEG channel. In some aspects, at least a portion of the charge compensation regions extend from below the gate electrode to make Ohmic contact with the source electrode. In some aspects, by extending the charge compensation regions from below the gate electrode and closer to the source and drain electrodes, the HEFTs can demonstrate avalanche characteristics. The HEMTs can include any suitable III-V semiconductor, and in particular can include a GaN semiconductor.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to, and the benefit of, U.S.provisional application entitled “HIGH ELECTRON MOBILITY TRANSISTORSWITH CHARGE COMPENSATION” having Ser. No. 62/851,367, filed May 22,2019, the contents of which are incorporated by reference in theirentirety.

TECHNICAL FIELD

The present disclosure generally relates to high electron-mobilitytransistors.

BACKGROUND

Improved power devices are highly desired for high-efficiencyelectricity generation and conversion. Applications of power devicesinclude power supplies, automotive electronics, motor controls anddrives, data centers, telecommunication circuits, display drives andmobile power management, for example. Such systems rely on efficientconverters to step-up or step-down electric voltages and convert betweenAC and DC signals. Power transistors capable of blocking a certainvoltage and carrying a certain current are key building blocks for suchconverters.

Conventional power devices (e.g. transistors or diodes) used in suchapplications are mainly made of silicon. However, the limited breakdownvoltage of silicon and its higher resistance make the commercial devicesand circuits currently available very bulky, heavy and operate at lowfrequencies. Thanks to the superior physical properties of galliumnitride (GaN), e.g. high critical electric field, excellent transportproperties, and high-temperature capability, compared to silicon,nitride power devices are widely perceived as excellent candidates forthe next-generation of high-frequency and high-efficient powerapplications. Nitride power devices have potentials to realize over100-fold lower on-resistance compared to silicon power devices with asimilar voltage class. This could greatly reduce the device power lossin power switching applications.

Currently, nitride-based high electron mobility transistors (HEMTs)which utilize a two-dimensional-gas (2DEG) channel, have been regardedas one of the most promising candidates for high-efficiency andhigh-frequency applications. The electron mobility of the 2DEG channelis at least ten-fold higher than that in conventionalmetal-oxide-semiconductor (MOS) channel. This enables lower deviceresistance and power loss.

Despite the tremendous potential of HEMTs, there are several technicalproblems that remain to be resolved. For example, reliable formation ofnormally-off transistors without increasing the device on-resistanceremains a challenge with nitride-based high electron mobilitytransistors. Nitride transistors which do not allow current to flow inthe absence of an applied gate voltage are desirable to simplify circuitdesign and to enable fail-safe operation in power electronics. However,existing attempts to solve this problem have resulted in sacrificing anincreased device resistance to achieve the desired device normally-offoperation. A second problem with existing nitride-based high electronmobility transistors is the realization of rugged breakdown voltage withavalanche capability. Avalanche is an impact ionization phenomenon thatallows a device to dissipate surge energy in abnormal circuit events.The lack of avalanche capability in nitride transistors significantlyundermines the device ruggedness. Novel device designs that enable theavalanche breakdown in nitride HEMTs are therefore highly desired.

There remains a need for improved high electron mobility transistorsthat overcome the aforementioned deficiencies such as formingnormally-off transistors without sacrificing the device resistance andtransistors which demonstrate avalanche breakdown.

SUMMARY

Described herein are a variety of HEMT structures that overcome one ormore of the aforementioned problems. In particular aspects, HEMT devicesare provided where the 2DEG channel is preserved in the gate region withhigh electron concentrations at low gate bias. This is advantageous fornitride HEMTs, especially for low-voltage (e.g. below 100 V) deviceswhere the resistance in the gate region becomes a main contributor tothe total device resistance. In addition, in some aspects, HEMT devicesare provided that enable the avalanche breakdown.

In some aspects, a high electron mobility transistor (HEMT) device isprovided having a plurality of active semiconductor layers formed on asubstrate, the plurality of active semiconductor layers comprising atleast a III-V semiconductor layer and a barrier layer, wherein a twodimensional electron gas (2DEG) is formed at a heterointerface betweenthe III-V semiconductor layer and the barrier layer; source and drainelectrodes each formed in Ohmic contact with the 2DEG; a gate electrodepositioned above the barrier layer between the source electrode and thegate electrode; and a plurality of charge-compensation regions below thegate electrode, wherein the charge-compensation regions comprise ap-type material and extend through the barrier layer and at leastpartially through the III-V semiconductor layer.

Other systems, methods, features, and advantages of HMETs will be orbecome apparent to one with skill in the art upon examination of thefollowing drawings and detailed description. It is intended that allsuch additional systems, methods, features, and advantages be includedwithin this description, be within the scope of the present disclosure,and be protected by the accompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

Further aspects of the present disclosure will be readily appreciatedupon review of the detailed description of its various embodiments,described below, when taken in conjunction with the accompanyingdrawings.

FIGS. 1A-1D depict schematics of four main E-mode technologies developedfor nitride HEMTs: FIG. 1A depicts a p-(Al)GaN gate. FIG. 1B depicts agate recess. FIG. 1C depicts a charge engineering HEMT. FIG. 1D depictsa cascode HEMT configuration.

FIGS. 2A-2E are simplified diagrams illustrating various exemplaryGaN-based HEMTs with charge compensation structures. FIG. 2A is a 3-Ddiagram of a first exemplary GaN-based HEMT according to variousaspects. FIG. 2B is a perspective diagram of semiconductor regions ofthe first exemplary GaN-based HEMT. FIG. 2C is a cross-sectional diagramof the first exemplary GaN-based HEMT along the cutline A-A′ in FIG. 2A.FIG. 2D is a simplified cross-sectional diagram illustrating a secondexemplary GaN-based HEMT. FIG. 2E is a simplified cross-sectionaldiagram illustrating a third exemplary GaN-based HEMT.

FIGS. 3A-3D are simplified diagrams illustrating various exemplaryGaN-based HEMTs with improved electric field management. FIG. 3A is a3-D diagram of a fourth exemplary GaN-based HEMT. FIG. 3B is aperspective diagram of semiconductor regions of the fourth exemplaryGaN-based HEMT. FIG. 3C is a top view of semiconductor regions of thefourth exemplary GaN-based HEMT. FIG. 3D is a schematic illustration ofelectric field distribution in the fourth exemplary GaN-based HEMT alongthe cutline B-B′ in FIG. 3C, comparing the electric field distributionwith (solid line) and without (dashed line) the charge-compensationregions 25.

FIGS. 4A-4C are simplified top-view diagrams illustrating variousexemplary aspects of the GaN-based HEMTs with avalanche breakdowncapability. FIG. 4A is a top-view diagram of a fifth exemplary GaN-basedHEMT. FIG. 4B is a top-view diagram of a sixth exemplary GaN-based HEMT.FIG. 4C is a top-view diagram of a seventh exemplary GaN-based HEMT.

FIGS. 5A-5C depicts simplified top-view diagrams illustrating variousexemplary aspects of the E-mode GaN-based HEMTs with avalanche breakdowncapability. FIG. 5A is a top-view diagram of an eighth exemplaryGaN-based HEMT. FIG. 5B is a top-view diagram of a ninth exemplaryGaN-based HEMT. FIG. 5C is a top-view diagram of a tenth exemplaryGaN-based HEMT.

FIG. 6 depicts a diagram of a GaN-based transistor structures from Ref.[20].

DETAILED DESCRIPTION

The development of improved nitride transistors has faced a variety ofchallenges. The first challenging problem is the reliable formation ofnormally-off transistors without increasing the device on-resistance.The normally-off is referred to herein as enhancement mode or E-mode,and the normally-on as depletion mode or D-mode. E-mode nitridetransistors, which do not allow current to flow in the absence of anapplied gate voltage, are desirable to simplify circuit design and toenable fail-safe operation in power electronics. Currently, four maintechnologies have been developed to make E-mode nitride HEMTs, i.e.p-(Al)GaN gate [1]-[6] (FIG. 1A), gate recess [7][8] (FIG. 1B), chargeengineering [9]-[12] (FIG. 1C) and Cascode configuration [13]-[15] (FIG.1D). All of these technologies realize the device normally-off operationat the price of an increased device resistance. The first threetechnologies significantly increase the channel resistance in the gateregion. In the first approach, the insertion of thick p-(Al)GaN layerreduces the gate capacitance, leading to smaller electron densitiesunder the gate. In the second approach, the 2DEG channel is replacedwith a MOS channel under gate, leading to a much lower electron mobilityunder gate. In the third approach, the introduced negative chargesreduce the electron densities under gate. In the fourth approach, thesilicon MOSFET introduces additional resistance to the cascoded D-modeHEMT. The technologies have not been able to demonstrate an E-modetransistor where the 2DEG channel is preserved in the gate region with arelatively large gate capacitance. The relatively large gate capacitanceis desired for nitride HEMTs, especially for low-voltage (e.g. below 100V) devices where the resistance in the gate region becomes a maincontributor to the total device resistance.

A second challenge faced by existing nitride HEMTs is the realization ofrugged breakdown voltage with avalanche capability. When the nitrideHEMT is biased close to its breakdown voltage, the electric fielddistribution is highly non-uniform with a peak value in semiconductorsnear the drain-side edge of the gate. As the HEMT channel is n-type andthere is no p-type region close to the peak electric field locations,the excess holes generated in the impact ionization cannot beeffectively removed. As a result, existing nitride HEMTs do not haveavalanche capability and typically show a destructive breakdown. Incontrast, most of silicon and silicon carbide power MOSFETs haveavalanche breakdown. The avalanche capability allows power devices todissipate the excess energy in inductive loads without catastrophicdevice failure during some overload power switching transients, andtherefore provides the device ruggedness for many power electronicsapplications, such as motor drive applications. The lack of avalanchecapability in nitride transistors significantly undermines the deviceruggedness.

Described herein are a variety of HEMT structures that overcome one ormore of the aforementioned problems. In particular aspects, HEMT devicesare provided where the 2DEG channel is preserved in the gate region witha high electron concentrations at low gate bias. This is advantageousfor nitride HEMTs, especially for low-voltage (e.g. below 100 V) deviceswhere the resistance in the gate region becomes a main contributor tothe total device resistance. In addition, in some aspects, HEMT devicesare provided that enable the avalanche breakdown.

In some aspects, HEMT devices are provided having p-typecharge-compensation structures in the close vicinity of the 2DEGchannels in nitride HEMTs. In some aspects, alternating p-typecharge-compensation structures and 2DEG channels are implemented in thegate region. In some aspects, a nitride HEMT is provided with uniformelectric field distribution at off-state biases. In certain aspects,p-type charge-compensation structures are implemented in thesemiconductor channel regions between gate and drain. A nitride HEMT canalso be provided in some aspects with avalanche breakdown and improvedruggedness. In these aspects, p-type charge-compensation structures areimplemented between source and drain and form electronic contact withthe source electrode. These various aspects solve some most challengingproblems of nitride HEMTs.

Before the present disclosure is described in greater detail, it is tobe understood that this disclosure is not limited to particularembodiments described, and as such may, of course, vary. It is also tobe understood that the terminology used herein is for the purpose ofdescribing particular embodiments only, and is not intended to belimiting. The skilled artisan will recognize many variants andadaptations of the embodiments described herein. These variants andadaptations are intended to be included in the teachings of thisdisclosure.

All publications and patents cited in this specification are cited todisclose and describe the methods and/or materials in connection withwhich the publications are cited. All such publications and patents areherein incorporated by references as if each individual publication orpatent were specifically and individually indicated to be incorporatedby reference. Such incorporation by reference is expressly limited tothe methods and/or materials described in the cited publications andpatents and does not extend to any lexicographical definitions from thecited publications and patents. Any lexicographical definition in thepublications and patents cited that is not also expressly repeated inthe instant specification should not be treated as such and should notbe read as defining any terms appearing in the accompanying claims. Thecitation of any publication is for its disclosure prior to the filingdate and should not be construed as an admission that the presentdisclosure is not entitled to antedate such publication by virtue ofprior disclosure. Further, the dates of publication provided could bedifferent from the actual publication dates that may need to beindependently confirmed.

Although any methods and materials similar or equivalent to thosedescribed herein can also be used in the practice or testing of thepresent disclosure, the preferred methods and materials are nowdescribed. Functions or constructions well-known in the art may not bedescribed in detail for brevity and/or clarity. Embodiments of thepresent disclosure will employ, unless otherwise indicated, techniquesof nanotechnology, organic chemistry, material science and engineeringand the like, which are within the skill of the art. Such techniques areexplained fully in the literature.

It should be noted that ratios, concentrations, amounts, and othernumerical data can be expressed herein in a range format. It is to beunderstood that such a range format is used for convenience and brevity,and thus, should be interpreted in a flexible manner to include not onlythe numerical values explicitly recited as the limits of the range, butalso to include all the individual numerical values or sub-rangesencompassed within that range as if each numerical value and sub-rangeis explicitly recited. To illustrate, a numerical range of “about 0.1%to about 5%” should be interpreted to include not only the explicitlyrecited values of about 0.1% to about 5%, but also include individualvalues (e.g., 1%, 2%, 3%, and 4%) and the sub-ranges (e.g., 0.5%, 1.1%,2.2%, 3.3%, and 4.4%) within the indicated range. Where the stated rangeincludes one or both of the limits, ranges excluding either or both ofthose included limits are also included in the disclosure, e.g. thephrase “x to y” includes the range from ‘x’ to ‘y’ as well as the rangegreater than ‘x’ and less than ‘y’. The range can also be expressed asan upper limit, e.g. ‘about x, y, z, or less’ and should be interpretedto include the specific ranges of ‘about x’, ‘about y’, and ‘about z’ aswell as the ranges of ‘less than x’, less than y′, and ‘less than z’.Likewise, the phrase ‘about x, y, z, or greater’ should be interpretedto include the specific ranges of ‘about x’, ‘about y’, and ‘about z’ aswell as the ranges of ‘greater than x’, greater than y′, and ‘greaterthan z’. In some embodiments, the term “about” can include traditionalrounding according to significant figures of the numerical value. Inaddition, the phrase “about ‘x’ to ‘y’”, where ‘x’ and ‘y’ are numericalvalues, includes “about ‘x’ to about ‘y’”.

In some instances, units may be used herein that are non-metric ornon-SI units. Such units may be, for instance, in U.S. CustomaryMeasures, e.g., as set forth by the National Institute of Standards andTechnology, Department of Commerce, United States of America inpublications such as NIST HB 44, NIST HB 133, NIST SP 811, NIST SP 1038,NBS Miscellaneous Publication 214, and the like. The units in U.S.Customary Measures are understood to include equivalent dimensions inmetric and other units (e.g., a dimension disclosed as “1 inch” isintended to mean an equivalent dimension of “2.5 cm”; a unit disclosedas “1 pcf” is intended to mean an equivalent dimension of 0.157 kN/m³;or a unit disclosed 100° F. is intended to mean an equivalent dimensionof 37.8° C.; and the like) as understood by a person of ordinary skillin the art.

It will be understood that, although the terms “first”, “second”, etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another element, component, region, layer or section. Thus,a first element, component, region, layer or section discussed belowcould be termed a second element, component, region, layer or sectionwithout departing from the teachings of example embodiments.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

Definitions

Unless defined otherwise, all technical and scientific terms used hereinhave the same meaning as commonly understood by one of ordinary skill inthe art to which this disclosure belongs. It will be further understoodthat terms, such as those defined in commonly used dictionaries, shouldbe interpreted as having a meaning that is consistent with their meaningin the context of the specification and relevant art and should not beinterpreted in an idealized or overly formal sense unless expresslydefined herein.

The articles “a” and “an,” as used herein, mean one or more when appliedto any feature in embodiments of the present invention described in thespecification and claims. The use of “a” and “an” does not limit themeaning to a single feature unless such a limit is specifically stated.The article “the” preceding singular or plural nouns or noun phrasesdenotes a particular specified feature or particular specified featuresand may have a singular or plural connotation depending upon the contextin which it is used.

High Electron Mobility Transistors

The majority of existing E-mode technologies involve the reduction of2DEG density or mobility in the whole area below the gate electrode. Forexample, p-(Al)GaN gate technologies [1]-[4][6][10][11] lay p-typelayers and other charge-compensation structures on top of or within theentire heterostructures in the gate region. This can be contrasted tovarious aspects of the current disclosure which introduce chargecompensation structures selectively in the gate region and thecharge-compensation regions are located aside the 2DEG channel ratherthan on top of the 2DEG channel. Gate recess technologies [7] thin downor completely remove the barrier layer in the whole gate region. Incomparison, the various aspects described herein can preserve thecomplete barrier layer in the partial gate region. Reference [16]selectively removes the heterostructure in the gate region. Incomparison, aspects described herein do not involve thesecharge-compensation structures.

References [17]-[19] describes III-nitride FETs with a p-typeback-barrier layer below the n-type channel. Reference. [17] describesIII-nitride HEMTs with a p-type back-barrier below the 2DEG channelextending laterally from the source to the gate. Reference [18]describes III-nitride HEMTs with a p-type back-barrier below the 2DEGchannel extending laterally from the source to the drain. Reference [19]describes III-nitride HEMTs with a p-type diamond back-barrier. In theaspects described in the current disclosure, the charge-compensationregions are located aside the 2DEG channel rather than below the 2DEGchannel.

Reference [20] describes III-nitride HEMTs with a plurality ofalternating p-GaN and n-GaN channels, as shown in the FIG. 6 whereas inthe aspects described in the instant disclosure the barrier layer(AlGaN) on top of p-GaN is not removed, which cannot completely removethe 2DEG channel in the charge-compensation regions and undermine thecharge compensation effects. In Reference [20], the charge compensationis established between the p-GaN bands and n-GaN bands while the chargecompensation is established between the p-type regions and the 2DEGchannel in the aspects described herein. In addition, the p-type regionsin Reference [20] do not form contact to any electrodes (source, gateand drain) and therefore cannot enable the hole removal and deviceavalanche capability.

Reference [21] describes III-nitride HEMTs with a plurality ofalternating p-AlGaN and n-AlGaN bands on top of the AlGaN barrier layerwhereas the p-type regions described in the instant disclosure do notextend downwards into the GaN channel region in [21]. As a result, 2DEGare present under the p-type regions in [21], while the 2DEG iscompletely removed in the p-type regions in various aspects of thedevices described herein.

As described in more detail herein, HEMTs are providing operating inE-mode. HEMTs are also provided having improved electric fieldmanagement. HEMTs are also provided having avalanche capability. In someaspects, the HEMTs are group III-V semiconductor HEMTs. In some aspects,the HEMTs described herein are GaN HEMTs.

E-Mode HEMTs

FIGS. 2A-2C show simplified diagrams illustrating one embodiment of thenitride HEMTs with charge compensation structures. The region 10 is asubstrate layer, such as GaN, silicon carbide, silicon, sapphire,diamond and AlN. Region 11 may be composed of a single layer or multiplebuffer layers, including adhesion, nucleation, transition and otherlayers for promoting the growth of the compound semiconductor epitaxiallayers on lattice-mismatched substrates. The materials of region 11 canbe binary III-V materials such as AlN or GaN, ternary III-V materialssuch as InGaN and AlGaN, and quaternary III-V materials such as AlInGaN.In some embodiments, the transition layers in region 11 can besuperlattice structure and compositionally-graded layers.

A III-V semiconductor layer 12 is disposed on the said region 11, withan exemplary thickness of 100 nm to 10 μm. In some embodiments, thematerials of layer 12 can be III-nitride or III-arsenide materials. Thesaid layer 12 may be low-level n-type doped, un-intentionally doped, orp-type doped, but preferably as un-intentionally doped or low-leveln-type doped. A III-V barrier layer 13 is disposed on the said III-Vsemiconductor layer 12, with an exemplary thickness of 5 nm to 100 nm.The material of layer 13 has a different lattice constant and bandgapenergy compared to material of layer 12. In some embodiments, thematerial of layer 13 has larger bandgap energy than the material oflayer 12, and a 2DEG channel 14 is formed at the heterostructure oflayer 13 and layer 12. In a specific embodiment, materials of layer 13and layer 12 can be InAlGaN and GaN, AlGaN and GaN, AlN and GaN, orInGaN and GaN.

A plurality of semiconductor regions 15 are formed extending downwardthrough the layer 13 into the layer 12. Region 15 has a conductivitytype opposite to the region 12 and the 2DEG channel 14, preferably asp-type doped. Region 15 can be doped with p-type dopants such asMagnesium (Mg) with an exemplary doping density of 1×10¹⁶ cm⁻³ to 1×10²¹cm⁻³. The material of region 15 can be identical to the material of thelayer 12 or the material of the layer 13, such as GaN, AlGaN, InGaN,InAlN, diamond and boron nitride. The material of region 15 can also bep-type oxides, such as nickel oxide and copper oxide. An exemplarythickness of region 15 is 10 nm to 2 μm and an exemplary width of region15 (along the A-A′ direction) is 50 nm to 10 μm. The spacing between thetwo neighboring region 15 can be identical or different from the widthof region 15, with an exemplary spacing of 50 nm to 10 μm. The saidspacing between the two neighboring region 15 can be identical in thewhole device region and can also vary. According to some embodiments,various methods can be adopted for the formation of region 15, includingbut not limiting to selective-area epitaxy in etched trenches, ionimplantation, sputtering and chemical vapor deposition (CVD). Theselective-area epitaxy can be implemented by using dielectric or metalmasks through various epitaxy technologies, such as CVD, metal-organicchemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) ormetal-organic vapor phase epitaxy (MOVPE).

16, 17, and 18 are the source electrode, gate electrode and drainelectrode for the HEMT. The source and drain electrodes 16 and 18 form aconnection (e.g. Ohmic contact) to the 2DEG at the heterostructure. Thesaid gate electrode 17 partially or completely overlaps with theplurality of regions 15. The device threshold voltage is positive. Atzero gate bias, the 2DEG channels under gate are depleted by theneighboring regions 15 in the lateral direction, such to enable thenormally-off operation.

FIGS. 2C-2D show the cross-sectional diagrams of the device structurealong the A-A′ direction in the gate region, for three differentembodiments. In some embodiments (FIG. 2C), the gate layer 17 formsdirect contact to the semiconductor layer 13 and the semiconductorregions 15. The gate metal can form a Schottky contact to the layer 13and can form either Schottky or Ohmic contact to the region 15. In someembodiments (FIG. 2D), a dielectric layer 19 is disposed on the layer 13and the regions 15 below the gate electrode 17, forming ametal-insulator-semiconductor (MIS) or a MOS gate stack to both layer 13and regions 15. The materials of regions 19 may include but is notlimited to SiO₂, Si_(x)N_(y), Si_(x)O_(y)N_(z)H_(w), Al₂O₃, HfO₂, etc.In some embodiments (FIG. 2E), the dielectric layer 19 is only disposedon top of layer 13 and is removed on top of regions 15. The gateelectrode 17 forms the MIS or MOS gate stack to the 2DEG channel andforms Schottky or Ohmic contact to the charge-compensation regions 15.

HEMTs with Improved Electric Field Management

FIGS. 3A-3C show the simplified diagrams illustrating one embodiment ofthe GaN-based HEMTs with improved electric field management. In thisembodiment, a plurality of p-type regions 25 are formed extendingdownward through the layer 13 into the layer 12. The plurality ofregions 25 partially overlaps with the gate electrode 17 and extendslaterally into the area between gate and drain. A plurality ofalternating p-doped regions 25 and 2DEG heterostructures are formed inat least part of the gate-to-drain area. The length of regions 25 couldbe larger than the length of the gate electrode 17 (L_(G)) and smallerthan the sum of L_(G) and gate-to-drain distance. The ranges of thewidth and depth of region 25 and the spacing between two neighboringregions 25 could be identical to the region 15 in the embodiment #1.

The design principle for the regions 25 is to realize the charge balancewith the 2DEG channel 14. Four parameters, the width (w), depth (t) anddoping concentration (N_(A)) of each region 25 as well as the spacing(s) between two neighboring regions 25, are key factors for the optimaldesign. The optimal design could meet the following relations:n _(2DEG) ·s=N _(A) ·t·wwhere n_(2DEG) is the 2DEG density (cm⁻²).

FIG. 3D shows the schematic distribution of electric field along theoutline B-B′ with (solid line) and without (dashed line) thecharge-compensation regions 25. The incorporation of regions 25 reshapesthe electric field distribution in 2DEG channels at high off-state drainbiases. For the same drain bias, the peak electric field at thedrain-side edge of the gate is reduced and the electric fielddistribution in the gate-to-drain area is much more uniform. Withoptimal designs, the electric field distribution between the gateelectrode and drain electrode could be completely uniform. For the samegate-to-drain distance, the device breakdown voltage could be higherwith the incorporation of regions 25.

HEMTs with Avalanche Capability

FIGS. 4A-4C show the simplified diagrams illustrating three embodimentsof the GaN-based HEMTs with the avalanche breakdown capability. In theseembodiments, the source electrode 16 forms Ohmic contacts to the 2DEGchannel 14 and the plurality of p-type regions 35 (or 45, 55)simultaneously. The plurality of p-type regions extends laterally to thedrain-side gate edges, where the peak electric field locates. At highdrain bias, the electrons and holes generated during the impactionization can be effectively removed, where the electrons are removedthrough the 2DEG channel and the drain electrode and the holes areremoved through the p-type charge-compensation structures and the sourceelectrode. Avalanche capability is therefore enabled in HEMTs. Thep-type semiconductor regions are designed to achieve the charge balancewith the 2DEG channel, similar to the design in the embodiment #2.

In some embodiments, as shown in FIG. 4A, the plurality of p-typeregions 35 extends laterally to the drain-side edge of the gateelectrode 17. In some embodiments, as shown in FIG. 4B, the plurality ofp-type semiconductor regions 45 extends laterally into the gate-to-drainregions. In some embodiments, as shown in FIG. 4C, the plurality ofp-type semiconductor regions 55 extends laterally to the drain electrode18 and can form either Ohmic contacts or Schottky contacts to the drainelectrode 18. In all these three embodiments, the plurality of p-typesemiconductor regions form Ohmic contact to the source electrode 16.

The HEMTs with avalanche capability shown in FIGS. 4A-4C could haveeither negative or positive threshold voltage, as thecharge-compensation designs for avalanche breakdown may not besufficient to deplete all 2DEG under the gate region at zero gate bias.FIGS. 5A-5C show simplified diagrams illustrating three embodiments withdenser plurality of charge-compensation structures under the gate, inthe same time having source-connected charge-compensation structures toallow for avalanche breakdown capability. In some embodiments, as shownin FIG. 5A, a plurality of p-type semiconductor regions 650 forms Ohmiccontacts to the source electrode 16 and extends laterally to thedrain-side edge of the gate electrode 17. An additional plurality ofp-type semiconductor regions 651 locate under the gate electrode 17. Insome embodiments, as shown in FIG. 5B, a plurality of p-typesemiconductor regions 750 forms Ohmic contacts to the source electrode16 and extends laterally into the gate-to-drain regions. An additionalplurality of p-type semiconductor regions 751 locate under the gateelectrode 17. In some embodiments, as shown in FIG. 5C, a plurality ofp-type semiconductor regions 850 forms Ohmic contacts to the sourceelectrode 16 and extends laterally to the drain electrode 18. Anadditional plurality of p-type semiconductor regions 851 locate underthe gate electrode 17.

Certain Aspects of the Disclosure

The disclosure will be better understood upon reading the followingaspects, which should not be confused with the claims. Any of theaspects described herein can, in some instances, be combined with othernumbered aspects below or with other aspects described elsewhere herein.

Aspect 1. A high electron mobility transistor (HEMT) device comprising:a plurality of active semiconductor layers formed on a substrate, theplurality of active semiconductor layers comprising at least a III-Vsemiconductor layer and a barrier layer, wherein a two dimensionalelectron gas (2DEG) is formed at a heterointerface between the III-Vsemiconductor layer and the barrier layer; source and drain electrodeseach formed in Ohmic contact with the 2DEG;

a gate electrode positioned above the barrier layer between the sourceelectrode and the gate electrode; a plurality of charge-compensationregions below the gate electrode, wherein the charge-compensationregions comprise a p-type material and extend through the barrier layerand at least partially through the III-V semiconductor layer.

Aspect 2. A high electron mobility transistor (HEMT) device comprising:a substrate; a semiconductor heterostructure channel region comprising abarrier layer including a first III-V semiconductor material and achannel layer including a second III-V semiconductor material, with thebandgap of said first III-V semiconductor larger than said second III-Vsemiconductor; a two-dimensional-electron-gas (2DEG) channel, formed insaid III-V heterostructure channel region; a source and a drain, whichform Ohmic contacts to said 2DEG channel; a gate; a plurality ofcharge-compensation semiconductor regions extending vertically throughsaid barrier layer into said channel layer, wherein saidcharge-compensation regions are doped with p-type dopants and are placedaside said 2DEG channel and do not overlap vertically with said 2DEGchannel; wherein at least a semiconductor region under the gate iscomprised of alternating said heterostructure channel regions and saidcharge-compensation regions.

Aspect 3. A high electron mobility transistor (HEMT) device comprising:a substrate; a semiconductor heterostructure channel region comprising abarrier layer including a first III-V semiconductor material and achannel layer including a second III-V semiconductor material, with thebandgap of said first III-V semiconductor larger than said second III-Vsemiconductor; a two-dimensional-electron-gas (2DEG) channel, formed insaid III-V heterostructure channel region; a source and a drain, whichform Ohmic contacts to said 2DEG channel; a gate; a plurality ofcharge-compensation semiconductor regions extending vertically throughsaid barrier layer into said channel layer, wherein saidcharge-compensation regions are doped with p-type dopants and are placedaside said 2DEG channel and do not overlap vertically with said 2DEGchannel; wherein the plurality of alternating heterostructure regionsand charge-compensation regions extend laterally from said source atleast to the drain-side gate edge.

Aspect 4. The HEMT according to any other aspect, wherein the III-Vsemiconductor layer has a first bandgap, and wherein the barrier layercomprises a second III-V semiconductor layer having a second bandgaplarger than the first bandgap.

Aspect 5. The HEMT according to any other aspect, wherein the substratecomprises a III-V semiconductor, silicon, diamond, sapphire, or acombination thereof.

Aspect 6. The HEMT according to any other aspect, further comprising abuffer layer.

Aspect 7. The HEMT according to any other aspect, wherein the bufferlayer comprises an adhesion layer, a nucleation layer, a transitionlayer, a layer for promoting the growth of the compound semiconductorepitaxial layers on lattice-mismatched substrates, a combinationthereof, or a combination with one or more additional layers.

Aspect 8. The HEMT according to any other aspect, wherein thecharge-compensation semiconductor regions comprise a p-type doped III-Vsemiconductor.

Aspect 9. The HEMT according to any other aspect, wherein one or more ofa doping level of the charge-compensation semiconductor regions, athickness of each of the charge-compensation semiconductor regions, anda spacing between adjacent charge-compensation semiconductor regions inthe plurality of charge-compensation semiconductor regions is designedsuch that charges in the 2DEG channel are nearly completely depletedwhen the HEMT is operated at a zero gate bias.

Aspect 10. The HEMT according to any other aspect, wherein one or moreof the III-V semiconductor layer, the barrier layer, and the p-typesemiconductor in the charge-compensation semiconductor regions areselected from InAlGaN and GaN, AlGaN and GaN, AlN and GaN, or InGaN andGaN.

Aspect 11. The HEMT according to any other aspect, wherein thecharge-compensation regions are made by a process comprisingtrench-filling epitaxy, ion implantation, sputtering or chemical vapordeposition.

Aspect 12. The HEMT according to any other aspect, wherein the chargecompensation regions extend at least across an entire gate regionextending under the gate electrode.

Aspect 13. The HEMT according to any other aspect, wherein the chargecompensation regions extend beyond the gate region.

Aspect 14. The HEMT according to any other aspect, wherein the chargecompensation regions extend at least from below the source electrode tobelow the gate electrode.

Aspect 15. The HEMT according to any other aspect, wherein the chargecompensation regions extend from below the source electrode to below thedrain electrode.

Aspect 16. The HEMT according to any other aspect, wherein the III-Vsemiconductor layer has a thickness of about 100 nm to about 10 microns.

Aspect 17. The HEMT according to any other aspect, wherein the barrierlayer has a thickness of about 5 nm to about 100 nm.

Aspect 18. The HEMT according to any other aspect, wherein a spacingbetween adjacent charge compensation regions in the plurality of chargecompensation regions is about 50 nm to about 10 μm, about 50 nm to about500 nm, about 1 μm to about 5 μm, or any combination thereof.

Aspect 19. The HEMT according to any other aspect, wherein a dopingdensity of the charge compensation regions is about 1×10¹⁶ cm⁻³ to about1×10²¹ cm⁻³.

Aspect 20. The HEMT according to any other aspect, wherein a thicknessof the charge compensation regions is about 10 nm to 1 μm.

Aspect 21. The HEMT according to any other aspect, wherein a thicknessof the charge compensation regions is larger than a thickness of thebarrier layer.

Aspect 22. The HEMT according to any other aspect, wherein the pluralityof charge compensation regions comprises a first plurality of chargecompensation regions extending from below the gate to make Ohmic contactwith the source electrode and a second plurality of charge compensationregions extending below the gate electrode but without making Ohmiccontact with the source electrode.

Aspect 23. The HEMT according to any other aspect, wherein the materialsof said charge-compensation regions include said first III-Vsemiconductor material, said second III-V semiconductor materials, otherIII-V semiconductor materials and diamond.

Aspect 24. The HEMT according to any other aspect, wherein the materialsof said barrier layer and channel layer include InAlGaN and GaN, AlGaNand GaN, AlN and GaN, or InGaN and GaN.

Aspect 25. The HEMT according to any other aspect, wherein saidcharge-compensation regions are made by trench-filling epitaxy or ionimplantation.

Aspect 26. The HEMT according to any other aspect, wherein thethickness, doping concentration and width of said charge-compensationregions as well as the spacing between neighboring charge-compensationregions are designed to completely deplete charges in the 2DEG channelat zero gate bias.

Aspect 27. The HEMT according to any other aspect, further comprising adielectric layer between said gate and the said semiconductor regioncomprising alternating heterostructure channel regions andcharge-compensation regions.

Aspect 28. The HEMT according to any other aspect, further comprising adielectric layer between said gate and the said heterostructure channelregions under said gate.

Aspect 29. The HEMT according to any other aspect, wherein the pluralityof alternating heterostructure regions and charge-compensation regionsextend laterally into the gate-to-drain region.

Aspect 30. The HEMT according to any other aspect, wherein the saidcharge-compensation regions are designed to realize the charge balancewith said 2DEG channel.

Aspect 31. The HEMT according to any other aspect, wherein the pluralityof alternating heterostructure regions and charge-compensation regionsextend laterally from said source at least to the drain-side gate edge;

Aspect 32. The HEMT according to any other aspect, wherein said sourceforms Ohmic contacts to said charge-compensation regions.

Aspect 33. The HEMT according to any other aspect, wherein the pluralityof alternating heterostructure regions and charge-compensation regionsextend laterally into the gate-to-drain regions.

Aspect 34. The HEMT according to any other aspect, wherein the pluralityof alternating heterostructure regions and charge-compensation regionsextend laterally from said source to said drain.

Aspect 35. The HEMT according to any other aspect, wherein the pluralityof charge-compensation regions form Ohmic or Schottky contacts to saiddrain.

Aspect 36. The HEMT according to any other aspect, wherein saidcharge-compensation regions are designed to realize the charge balancewith said 2DEG channel.

Aspect 37. The HEMT according to any other aspect, wherein the materialsof said charge-compensation regions include said first III-Vsemiconductor material, said second III-V semiconductor materials, otherIII-V semiconductor materials and diamond.

Aspect 38. The HEMT according to any other aspect, wherein the materialsof said barrier layer and channel layer include InAlGaN and GaN, AlGaNand GaN, AlN and GaN, or InGaN and GaN.

Aspect 39. The HEMT according to any other aspect, wherein saidcharge-compensation regions are made through trench-filling epitaxy orion implantation.

Aspect 40. The HEMT according to any other aspect, further comprising agate dielectric layer between said gate and said barrier layer.

Aspect 41. The HEMT according to any other aspect, wherein the width ofeach heterostructure band is smaller in the gate region compared to thewidth of heterostructure band in the source-to-gate region.

Aspect 42. The HEMT according to any other aspect, wherein the chargecompensation region makes Ohmic contact with the source electrode.

Aspect 43. The HEMT according to any other aspect, wherein the chargecompensation region makes Ohmic contact with the drain electrode.

Aspect 44. The HEMT according to any other aspect, wherein the p-typematerial comprises a p-type oxide such as nickel oxide or copper oxide.

REFERENCES

The following references are provided to assist in better understandingthe disclosure and technologies described therein. The citation of anypublication is for disclosure purposes only and should not be construedas an admission that the publication is material in any way topatentability of the claims nor that the present disclosure is notentitled to antedate such publication by virtue of prior disclosure.Further, the dates of publication provided could be different from theactual publication dates that may need to be independently confirmed.

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It should be emphasized that the above-described embodiments of thepresent disclosure are merely possible examples of implementations, andare set forth only for a clear understanding of the principles of thedisclosure. Many variations and modifications may be made to theabove-described embodiments of the disclosure without departingsubstantially from the spirit and principles of the disclosure. All suchmodifications and variations are intended to be included herein withinthe scope of this disclosure.

I claim:
 1. A high electron mobility transistor (HEMT) devicecomprising: a plurality of active semiconductor layers formed on asubstrate, the plurality of active semiconductor layers comprising atleast a III-V semiconductor layer and a barrier layer, wherein a twodimensional electron gas (2DEG) is formed at a heterointerface betweenthe III-V semiconductor layer and the barrier layer; source and drainelectrodes each formed in Ohmic contact with the 2DEG; a gate electrodepositioned above the barrier layer between the source electrode and thedrain electrode; a plurality of charge-compensation regions below thegate electrode, wherein the charge-compensation regions comprise ap-type material and extend through the barrier layer and at leastpartially through the III-V semiconductor layer, and wherein adjacentcharge-compensation regions of the plurality of charge-compensationregions are separated by non p-type regions of the III-V semiconductorlayer and non p-type regions of the barrier layer.
 2. The HEMT accordingto claim 1, wherein the III-V semiconductor layer has a first bandgap,and wherein the barrier layer comprises a second III-V semiconductorlayer having a second bandgap larger than the first bandgap.
 3. The HEMTaccording to claim 1, wherein the substrate comprises a III-Vsemiconductor, silicon, diamond, sapphire, or a combination thereof. 4.The HEMT according to claim 1, further comprising a buffer layer.
 5. TheHEMT according to claim 4, wherein the buffer layer comprises anadhesion layer, a nucleation layer, a transition layer, a layer forpromoting a growth of compound semiconductor epitaxial layers onlattice-mismatched substrates, a combination thereof, or a combinationwith one or more additional layers.
 6. The HEMT according to claim 1,wherein the p-type material comprises a p-type doped III-V semiconductoror a p-type oxide such as nickel oxide or copper oxide.
 7. The HEMTaccording to claim 1, wherein one or more of a doping level of thecharge-compensation regions, a thickness of each of thecharge-compensation regions, and a spacing between adjacentcharge-compensation regions in the plurality of charge-compensationregions is designed such that charges in the 2DEG are nearly completelydepleted when the HEMT is operated at a zero gate bias.
 8. The HEMTaccording to claim 1, wherein one or more of the III-V semiconductorlayer, the barrier layer, and the p-type material are selected fromInAlGaN and GaN, AlGaN and GaN, AlN and GaN, or InGaN and GaN.
 9. TheHEMT according to claim 1, wherein the charge-compensation regions aremade by a process comprising trench-filling epitaxy, ion implantation,sputtering or chemical vapor deposition.
 10. The HEMT according to claim1, wherein the charge compensation regions extend at least across anentire gate region extending under the gate electrode.
 11. The HEMTaccording to claim 10, wherein the charge compensation regions extendbeyond the gate region.
 12. The HEMT according to claim 10, wherein thecharge compensation regions extend at least from below the sourceelectrode to below the gate electrode, and wherein the chargecompensation regions make Ohmic contact with the source electrode. 13.The HEMT according to claim 10, wherein the charge compensation regionsextend from below the source electrode to below the drain electrode, andwherein the charge compensation regions make Ohmic contact with thesource electrode.
 14. The HEMT according to claim 1, wherein the III-Vsemiconductor layer has a thickness of about 100 nm to about 10 microns.15. The HEMT according to claim 1, wherein the barrier layer has athickness of about 5 nm to about 100 nm.
 16. The HEMT according to claim1, wherein a spacing between adjacent charge compensation regions in theplurality of charge compensation regions is about 50 nm to about 10 μm,about 50 nm to about 500 nm, about 1 μm to about 5 μm, or anycombination thereof.
 17. The HEMT according to claim 1, wherein a dopingdensity of the charge compensation regions is about 1×10¹⁶ cm⁻³ to about1×10²¹ cm⁻³.
 18. The HEMT according to claim 1, wherein a thickness ofthe charge compensation regions is about 10 nm to 1 μm.
 19. The HEMTaccording to claim 1, wherein a thickness of the charge compensationregions is larger than a thickness of the barrier layer.
 20. The HEMTaccording to claim 1, wherein the plurality of charge compensationregions comprises a first plurality of charge compensation regionsextending from below the gate to make Ohmic contact with the sourceelectrode and a second plurality of charge compensation regionsextending below the gate electrode but without making Ohmic contact withthe source electrode.